To create a 984 ladder logic network and evaluate system scan time.
The following example 984 ladder logic network can be used in your application program to evaluate system scan time. The addresses used here may or may not be available for use in your application. Please ensure all addresses chosen are currently unused in your existing application:
The up-counter counts 1000 scans as it transitions 500 times. When the counter has transitioned 500 times, the T.01 timer turns OFF and stores the number of hundredths of seconds it has taken for the counter to transition 500 times (1000 scans) in register 40003.
The value stored in 40002/40003 in the DIV block is then divided by 100 and the result, which represents logic solve time in ms, is stored in register 40005.
Note: 10001 is controlled via a DISABLE or a hard-wired input; if you are running the program in optimized mode, a hard-wired input is required to toggle 10001.
Note: The default maximum amount of time allowed for a scan is 250 ms; if the scan has not completed in that amount of time, a watchdog timer in the CPU stops the application and sends a timeout error message to the programming panel display. The maximum limit on scan time protects the PLC from entering into an infinite loop.
Note: The T.01 setting of #0999 will limit the scan time evaluation to 10 ms. If the scan time is to exceed this, some CPUs will allow a higher constant or you can simply replace the #0999 with a 4X register for any CPU and enter a much larger number into the register.